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Coders Brain Technology Pvt. Ltd.

<div><strong>Location: Bangalore/Noida</strong></div><div><br></div><div style="text-align: center;"><strong style="color: black;">Description:</strong></div><div style="text-align: center;"><span style="color: black;">Manage and lead a team of physical design engineers. Job also entails significant amount of hands-on work, in particular place-and-route, static timing analysis, formal verification, physical verification, and power analysis. Drive implementation of physical design methodologies as required through the development of automation scripts. Work with front-end engineers to resolve timing and power issues. Evaluate new tools, and creatively drive power reduction of designs. Must be proficient and highly capable in floorplanning and time budgeting.</span></div><div style="text-align: center;"><span style="color: black;">&nbsp;</span></div><div style="text-align: center;"><strong style="color: black;">&nbsp;</strong></div><div style="text-align: center;"><strong style="color: black;">Desired Skills &amp; Experience:</strong></div><div style="text-align: center;"><br></div><div style="text-align: center;"><span style="color: black;">Must possess 10+ years of hands on experience in handling block/chip level implementation from Netlist to GDS</span></div><div style="text-align: center;"><span style="color: black;">Must possess hands on experience in timing closure and physical verification closure</span></div><div style="text-align: center;"><span style="color: black;">Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz</span></div><div style="text-align: center;"><span style="color: black;">Experience in handling lower tech nodes that include 40nm, 28nm or lesser nodes etc.</span></div><div style="text-align: center;"><span style="color: black;">Must have hands on tapeout experience in lower tech nodes in any of the tools mentioned such ICC or SOC Encounter or mentor tools.</span></div><div style="text-align: center;"><span style="color: black;">Must have the ability to think on the spot for quick solutions and work-around at the time of tapeout to hit the schedule on time</span></div><div style="text-align: center;"><span style="color: black;">Must possess excellent scripting skills – TCL or Perl</span></div><div style="text-align: center;"><span style="color: black;">Experience in Synthesis and Formal is a plus</span></div><div style="text-align: center;"><span style="color: black;">Excellent verbal and written communication skills are required.</span></div><div style="text-align: center;"><span style="color: black;">Must possess excellent debug skills, analytical skills and the ability to work independently.</span></div><div style="text-align: center;"><span style="color: black;">Must be highly motivated and&nbsp;possess excellent team spirit</span></div><div style="text-align: center;"><span style="color: black;">&nbsp;</span></div><div style="text-align: center;"><span style="color: black;">&nbsp;</span></div><div style="text-align: center;"><strong style="color: black;">Primary Skills:</strong></div><div style="text-align: center;"><span style="color: black;">Ability to lead a team size of minimum of 10 members who can handle Subsystem PNR activities , Subsystem timing closure and&nbsp;Subsystem physical verification</span></div><div style="text-align: center;"><span style="color: black;">&nbsp;</span></div><div style="text-align: center;"><strong style="color: black;">Secondary Skills:</strong></div><div style="text-align: center;"><span style="color: black;">Knowledge in Subsystem Synthesis, Subsystem IR drop, Subsystem Lec, Subsystem CLP</span></div><div><br></div>