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<div><strong style="color: black;">STA (Static timing analysis) Engineers: 4 – 15 years</strong></div><div><strong>Location:bangalore</strong></div><div><strong>Skills:&nbsp;</strong></div><div>Experience in Synthesis of complex SoCs block/ top level and writing timing constraints.</div><div>Experience in formal verification RTL to netlist – to- netlist with DFT constraints.</div><div>Experience in post-layout STA closure and timing ECOs.</div><div>Worked in technology nodes 45 nm and below.</div><div>Knowledge of low -power aware implementation is a plus.</div><div>Tools: Design compiler, RTL compiler, LEC, CLP, ETS/ PTSI/ GT.</div><div>&nbsp;</div><div style="text-align: justify;"><strong>Primary Skills:</strong></div><div style="text-align: justify;"><strong>Able to handle Soc/Subsystem and blocklevel synthesis activities , Soc/Subsystem and blocklevel LEC, CLP and timing closure</strong></div><div style="text-align: justify;">&nbsp;</div><div style="text-align: justify;"><strong>Secondary Skills:</strong></div><div style="text-align: justify;"><strong>Able to handle PTPX and debug CTS issues to balance clocks</strong></div><div><br></div>