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Coders Brain Technology Pvt. Ltd.

<div><span style="color: rgb(0, 0, 0);">Role: STA lead&nbsp;</span></div><div><span style="color: rgb(0, 0, 0);">Location: Bangalore.</span></div><div><span style="color: rgb(0, 0, 0);">Experience: 5+ Y</span></div><div><span style="color: rgb(0, 0, 0);">Company Name: HCL</span></div><div><span style="color: rgb(0, 0, 0);">Notice Period : Immediate to 30 Days</span></div><div><br></div><div><span style="color: rgb(0, 0, 0);">Below is the&nbsp;JD for STA Lead 5+yrs.</span></div><div><br></div><div><span style="color: rgb(0, 0, 0);">&nbsp;</span></div><div><strong style="color: rgb(0, 0, 0);">STA / Synthesis (Design Implementation) Lead LD:</strong></div><div style="text-align: justify;"><span style="color: rgb(0, 0, 0);">●&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Hand-on Experience and Comprehensive knowledge of&nbsp;Synthesis and Static Timing Analysis.</span></div><div style="text-align: justify;"><span style="color: rgb(0, 0, 0);">●&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.</span></div><div style="text-align: justify;"><span style="color: rgb(0, 0, 0);">●&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Hands-on the DMSA flow to fix pre and post STA timing.</span></div><div style="text-align: justify;"><span style="color: rgb(0, 0, 0);">●&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Knowledge on the Timing closure on Sub system level &amp; Block level and Chip level.</span></div><div style="text-align: justify;"><span style="color: rgb(0, 0, 0);">●&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Knowledge on Writing Manual ECO’s to fix timing violations and DRC’s.</span></div><div style="text-align: justify;"><span style="color: rgb(0, 0, 0);">●&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Knowledge on constraint development.</span></div><div style="text-align: justify;"><span style="color: rgb(0, 0, 0);">●&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Good Knowledge of TCL scripting and UNIX env.</span></div><div style="text-align: justify;"><span style="color: rgb(0, 0, 0);">●&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Leading the team 4 to 5 team members by guiding and mentoring on the STA /Synthesis.</span></div><div style="text-align: justify;"><span style="color: rgb(0, 0, 0);">●&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Should Co-ordinate with design team counterparts in RTL design, Physical design and DFT.</span></div><div style="text-align: justify;"><span style="color: rgb(0, 0, 0);">●&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Good communication skills and client interface role</span></div>