Coders Brain is a global leader in it services, digital and business solutions that partners with its clients to simplify, strengthen and transform their businesses. We ensure the highest levels of certainty and satisfaction through a deep-set commitment to our clients, comprehensive industry expertise and a global network of innovation and delivery centers.

We achieved our success because of how successfully we integrate with our clients.

Coders Brain Technology Pvt. Ltd.

<div>Role: AMS Circuit design engineer</div><div>Exp: 3+ Y</div><div>Location: Bangalore</div><div>Notice Period: Immediate to 15 days</div><ul><li><span style="color: rgb(0, 0, 0);">The Analog/Mixed-Signal IP design team is looking for a Circuit Design Engineer to carry out the design and development for the next generation transceiver IOs, high-speed memory (LPDDR5, DDR5, gDDR6, HBM2/HBM3, etc.), and chip-to-chip Gbps proprietary PHY IP solutions.</span></li><li><span style="color: rgb(0, 0, 0);">&nbsp;As an Analog/Mixed-Signal Designer, your responsibilities include but not limited to the following:</span></li></ul><div>	<span style="color: rgb(0, 0, 0);">1.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Design and analyze mixed-signal circuit building blocks for PLL, DLL, and clock distribution to be used in the high-speed interfaces.</span></div><div><span style="color: rgb(0, 0, 0);">2.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Provide schematic layout guidance to mask designer and perform post-layout simulation.</span></div><div><span style="color: rgb(0, 0, 0);">3.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Pre-layout and post-layout design optimization to meet specifications across PVT, sensitivity, aging, electromigration simulation tests.</span></div><div><span style="color: rgb(0, 0, 0);">4.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Collaborate with layout engineers, RTL circuit designers to define IP sign-off requirements to ensure efficient IP integration.</span></div><div><span style="color: rgb(0, 0, 0);">5.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Define test plans and support for post-silicon IP bring-up, debug, validation, and characterization</span></div><div><span style="color: rgb(0, 0, 0);">6.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Interface with SOC teams, system HW/SW teams, and global manufacturing teams to specify component level requirements</span></div>