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Coders Brain Technology Pvt. Ltd.

<div><span style="font-size: 12px; color: rgb(33, 37, 41);">1. Experience in Low power RTL design, microarchitecture, synthesis, timing closure, power estimation. Should be proficient in Verilog. </span></div><div><span style="font-size: 12px; color: rgb(33, 37, 41);">2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus. </span></div><div><span style="font-size: 12px; color: rgb(33, 37, 41);">3. Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus. </span></div><div><span style="font-size: 12px; color: rgb(33, 37, 41);">4. Experience with hardware architecture exploration, performance modelling will be a big plus. 5. Prior experience in Machine learning/Artificial Intelligence domain and/or DRAM Memory controllers is a plus.</span></div>