INSURANCE POS | MEDICAL SUPPLY | HUMAN RESOURCE RECRUITMENT

Owen Mitten Private Limited

<div><span style="font-size: 14px; color: rgb(0, 0, 0);">Roles &amp; Responsibilities :</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Verification of ASIC, custom IC designs, and/or FPGA design</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Build and lead the verification team.</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Drive the test bench architecture, verification plan and test bench development for full chip and subsystem verification.</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Mentor and lead a team of verification engineers to complete unit, subsystem and chip level verification.</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Develop and maintain methodology, flows, and sign-off criteria for verification.</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">The Ideal Candidate :</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Experience with development of test bench architecture, test plan and test bench development for full chip and subsystem verification</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Hands on experience with System Verilog and VMM/OVM/UVM</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Hands-on experience with simulation tools including Synopsys VCS, Cadence IES to verify full-chip SoCs and FPGA based designs</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Requires strong understanding of state-of-the-art verification techniques, including assertion and metric-driven verification.</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Experience in AXI, DDR4, HBM, PCIe verification is a plus</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Verification experience in hardware accelerators and coprocessors is a plus</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Familiarity with verification management tools including regression management is required</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Familiarity with scripting in Python or Perl</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Strong understanding of ASIC and/or full custom chip development process is required</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Experience with FPGA programming and software is a plus</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Coherency and computer architecture experience is desirable</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.</span></div><div><br></div><div><span style="font-size: 14px; color: rgb(0, 0, 0);">- Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques are a plus</span></div>